Convey Computer is out with a new whitepaper that explains how their hybrid-core architecture is well suited to Big Data and Graph Computing:
As we have reviewed, solving graph problems takes a different approach to computing. One such approach is the Convey HC (hybrid-core) family of computer systems. The Convey systems offer a balanced architecture: reconfigurable (via Field Programmable Gate Arrays—FPGAs) compute elements, and a supercomputing-inspired memory subsystem (Figure 3).Figure 3. Overview of the Convey hybrid-core computing architecture.The benefit of hybrid-core computing is that the compute-intensive kernel of the Graph500 breadth-first search is implemented in hardware on the FPGAs in the coprocessor. The FPGA implementation allows much more parallelism than a commodity system (the Convey memory subsystem allows up to 8,192 outstanding concurrent memory references). The increase in parallelism combined with the hardware implementation of the logic portions of the algorithm allow for increased overall performance with much less hardware.
Download the PDF on this summary page.
Coming to SC11? This year, the Convey exhibit will include a ‘Graph Corner’ where you learn about the Graph500 benchmark and the company’s GraphConstructor. In addition, Bob Masson and Kirby Collins will present: “Heterogeneous Computing Architecture Supporting Applications in Data-intensive Sciences” on Thursday, November 17th, at 2:30 p.m. as part of the SC11 Exhibitor Forum.